1. Field of the Invention
The present invention relates to a device for electrostatic discharge (ESD) protection, and more particularly to a device for electrostatic discharge (ESD) protection with upgraded electrostatic discharge immunity when a reverse bias voltage is applied.
2. Description of the Related Art
Integrated circuit is frail and easy to be damaged during electrostatic discharge. Even though it maybe just a minor and temporary feeling for human body during electrostatic discharge, the damage resulting from the electrostatic discharge is unrecoverable and permanent. Electrostatic discharge could be present any moment during the manufacture process of integrated circuit chip, most of electrostatic discharge are present during the processes of forming integrated circuits on wafers or the stage of integrated circuit package.
In order to keep integrated circuits from being damaged by electrostatic discharge, additional devices are utilized to conduct hazardous electrostatic charges. These additional devices should not cause any harmful influence to the operation of the integrated circuit. Conventional devices include fuses, diodes or more complicated circuits such as grounded N type metal oxide semiconductor transistors or bipolar transistors.
FIG. 1 shows a conventional device for electrostatic discharge protecting integrated circuit. Diodes 106 and 108 for electrostatic discharge protection connect to a first power line to Vdd and a second power line to Vss ground respectively, wherein the diodes 106 and 108 are P+/N well diode and N+/P well diode. The diodes 106 and 108 connect between a bond pad 102 and an integrated circuit 104. The diodes 106 and 108 provide an electrostatic discharge path to release large amount of electrostatic charges. FIG. 2 shows a cross-sectional view of a conventional device for protecting integrated circuit from electrostatic discharge damage. The diode 106 comprises N+ diffusion region 204, P+ diffusion region 206 and N well 202. FIG. 2 also shows guard ring surrounding diodes as P+ diffusion regions 210 and 212. The conventional device for electrostatic discharge protection shown in FIGS. 1 and 2 has a drawback, which is the limited electrostatic discharge immunity under a reverse bias voltage. The areas occupied by the diodes 106 and 108 must be increased as large as possible in order to effectively release electrostatic current especially under ND mode and NS mode. However, a large layout area will be used or occupied in order to achieve this purpose. Therefore, it is a dilemma of maintaining the performance of the device for electrostatic discharge protection or saving the layout area of the integrated circuit being protected, and a compromise must be made between the performance of the device for electrostatic discharge protection and the layout area of the integrated circuit being protected. It is toward these goals that the present invention is specifically directed.